diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index 3b119e4..29b08f1 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -25,7 +25,7 @@
 		reg = <0x1e6e0000 0x174
 			0x1e6e0200 0x1d4 >;
 		#reset-cells = <1>;
-		clocks = <&scu PLL_MPLL>;
+		clocks = <&scu ASPEED_CLK_MPLL>;
 		resets = <&rst AST_RESET_SDRAM>;
 	};
 
@@ -39,7 +39,7 @@
 				compatible = "aspeed,ast2500-sdhci";
 				reg = <0x1e740100>;
 				#reset-cells = <1>;
-				clocks = <&scu BCLK_SDCLK>;
+				clocks = <&scu ASPEED_CLK_SDIO>;
 				resets = <&rst AST_RESET_SDIO>;
 			};
 
@@ -47,7 +47,7 @@
 				compatible = "aspeed,ast2500-sdhci";
 				reg = <0x1e740200>;
 				#reset-cells = <1>;
-				clocks = <&scu BCLK_SDCLK>;
+				clocks = <&scu ASPEED_CLK_SDIO>;
 				resets = <&rst AST_RESET_SDIO>;
 			};
 		};
@@ -56,23 +56,23 @@
 };
 
 &uart1 {
-	clocks = <&scu PCLK_UART1>;
+	clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
 };
 
 &uart2 {
-	clocks = <&scu PCLK_UART2>;
+	clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
 };
 
 &uart3 {
-	clocks = <&scu PCLK_UART3>;
+	clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
 };
 
 &uart4 {
-	clocks = <&scu PCLK_UART4>;
+	clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
 };
 
 &uart5 {
-	clocks = <&scu PCLK_UART5>;
+	clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
 };
 
 &timer {
@@ -80,9 +80,9 @@
 };
 
 &mac0 {
-	clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
+	clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
 };
 
 &mac1 {
-	clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
+	clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
 };